Brief Introduction
From zero to VHDL designer. Learn how to implement your VHDL design on FPGA starting from scratchDescription
****************************** UPDATE ***********************************
2020, Jan-09: add quiz in section 3
2018,April-08: Added quizzes on section2, updated caption up to lesson 10
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How many times do you waste your time in finding some examples useful to resolve your VHDL problems and didn't get anything useful?
YES, it is true that we can find a lot of information for free, but not all the information we get is good stuff. Many times we need a huge amount of time to filter good stuff from useless material. Even if we get the information for free, we often don't think about the time we are wasting and to the "equivalent money" we are losing wasting this time.
In Surf-VHDL, we have more than 20 years in the FPGA/ASIC VHDL design.
In this course, you will learn the basic rules to implement and efficient hardware design and how to apply these rules using VHDL.
Here what you will learn at the end of the course:
Entity / Architecture pair definition
Concurrency
VHDL Coding Style: Structural, Behavioral, Sequential
Event and Transaction
Delay Modeling: Inertial vs Transport delay
Concurrent Conditional Signal Assignment
Understanding Driver & Source concept
Parametric Design: Generics
VHDL Types and Data object
VHDL Types of Data Object: Signal, Variable, Constant and FILE
Type bit vs ulogic vs std_logic
Signed and Unsigned Data Types
Type Conversion and Type Casting
Subtype definition
Process Statement
Sequential Conditional Statement: IF and CASE
Sequential-Iterative Statement: FOR and WHILE
The Assert Statement
Sequential WAIT Statement
Sensitivity List vs WAIT Statement
Procedure and Function
Packages
Concurrent iterative Statement FOR GENERATE
Concurrent conditional Statement IF GENERATE
TextIO package: Read/Write from file
Test bench design and simulation
The most important section is the LAB section. This is the real value of this course.
In the LAB section, you will learn how to implement
Heart-bit design: let's start with a blinking led
Seven segment display: write a VHDL code and drive a seven-segment display
UART: learn how to implement a UART 16650 compatible with internal FIFO
Command Parser: VHDL design that contains the LABs above. Connect your board to a PC and start to communicate with it.
All the LABs are provided with the VHDL code that you have to complete and simulate.
In the LAB videos, there will be addressed the exercise solution: you will learn how to implement the lab VHDL code, simulate and layout on FPGA
Enjoy the course and start becoming a VHDL designer!
Requirements
- Requirements
- Basic of Boolean Algebra
- Basic notion of FPGA and Electronics
- Knowledge of Hex and Binary notation
- Desire to Learn!
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