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VLSI CAD Part II: Layout

Approx. 24 hours to complete

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Course Summary

This course teaches the fundamental concepts and techniques used in VLSI CAD layout design. Participants will learn how to design and implement digital circuits using state-of-the-art CAD tools.

Key Learning Points

Learn about the basics of VLSI design and layout
Understand the different stages of VLSI design
Get hands-on experience with industry-standard CAD tools

Job Positions & Salaries of people who have taken this course might have

- USA: $97,000
- India: ₹1,200,000
- Spain: €40,000
- USA: $97,000
- India: ₹1,200,000
- Spain: €40,000
- USA: $103,000
- India: ₹1,500,000
- Spain: €45,000
- USA: $97,000
- India: ₹1,200,000
- Spain: €40,000
- USA: $103,000
- India: ₹1,500,000
- Spain: €45,000
- USA: $112,000
- India: ₹1,800,000
- Spain: €55,000

Learning Outcomes

Understand the principles of VLSI design and layout
Be able to use industry-standard CAD tools for layout design
Design and implement digital circuits using advanced techniques

Prerequisites or good to have knowledge before taking this course

Basic knowledge of digital circuits
Familiarity with programming languages

Course Difficulty Level

Intermediate

Course Format

Self-paced
Online

Similar Courses

Digital Integrated Circuits
Introduction to Digital Systems
Advanced VLSI CAD

Related Education Paths

Related Books

Description

You should complete the VLSI CAD Part I: Logic course before beginning this course.

A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class).

Outline

Orientation
Welcome and Introduction
Two Tools Tutorial
Syllabus
Tools For This Course
Demographics Survey

ASIC Placement
Basics
Wirelength Estimation
Simple Iterative Improvement Placement
Iterative Improvement with Hill Climbing
Simulated Annealing Placement
Analytical Placement: Quadratic Wirelength Model
Analytical Placement: Quadratic Placement
Analytical Placement: Recursive Partitioning
Analytical Placement: Recursive Partitioning Example
Week 1 Overview
Week 1 Assignments

Technology Mapping
Technology Mapping Basics
Technology Mapping as Tree Covering
Technology Mapping—Tree-ifying the Netlist
Technology Mapping—Recursive Matching
Technology Mapping—Minimum Cost Covering
Technology Mapping—Detailed Covering Example
Week 2 Overview
Week 2 Assignments
Problem Set #1

ASIC Routing
Routing Basics
Maze Routing: 2-Point Nets in 1 Layer
Maze Routing: Multi-Point Nets
Maze Routing: Multi-Layer Routing
Maze Routing: Non-Uniform Grid Costs
Implementation Mechanics: How Expansion Works
Implementation Mechanics: Data Structures & Constraints
Implementation Mechanics: Depth First Search
From Detailed Routing to Global Routing
Week 3 Overview
Week 3 Assignments
Problem Set #2

Timing Analysis
Basics
Logic-Level Timing: Basic Assumptions & Models
Logic-Level Timing: STA Delay Graph, ATs, RATs, and Slacks
Logic-Level Timing: A Detailed Example and the Role of Slack
Logic-Level Timing: Computing ATs, RATs, Slacks, and Worst Paths
Interconnect Timing: Electrical Models of Wire Delay
Interconnect Timing: The Elmore Delay Model
Interconnect Timing: Elmore Delay Examples
Week 4 Overview
Week 4 Assignments
Problem Set #3

Final Exam
Problem Set #4
Final Exam
End of Course Survey

Summary of User Reviews

This VLSI CAD Layout course has received positive feedback from users. Many learners appreciated the comprehensive approach of the course in teaching VLSI CAD Layout.